1. Field of the Invention
The present invention relates to a level converting method and a level converting circuit and, more particularly, to the level converting method and circuit suitable for converting an output level of a CMOS (Complementary Metal Oxide Semiconductor) logic circuit to an input level of an ECL (Emitter-Coupled Logic) logic circuit.
2. Description of the Related Art
Such a signal transmission system has been so far known that supplies a CMOS logic circuit's output level via a transmission line to an ECL logic circuit. Since the CMOS logic circuit and the ECL logic circuit have mutually different signal levels (hereinafter referred to as logic levels) of their own, to supply a signal output from the CMOS logic circuit via the transmission line to the ECL logic circuit in order to permit that ECL logic circuit to operate predetermined logic operations, it is necessary to convert the logic level of the signal output from the CMOS logic circuit to the logic level of the ECL logic circuit and then supply thus obtained signal to that ECL logic circuit.
In a prior-art example shown in FIG. 4, a CMOS logic circuit 12 which outputs a logic signal to be level-shifted is connected somewhere between a positive power supply V.sub.DD (typically 5.0V or 3.3V) and a ground potential, to perform full-swing operations between the V.sub.DD and the ground potential when the logic signal is applied to its input. Then, an ECL logic circuit 26 which receives thus level-shifted logic signal is connected somewhere between the ground potential and a negative power supply V.sub.EE (typically -5.2V or -4.5V), so that in such a state where a DC (Direct Current) bypass set as a value adapted to perform a logic decision on an input logic signal is applied to its input terminal, it performs logic operations based on the input logic signal at a logic level between the ground potential and the negative power supply V.sub.EE.
To level-shift the logic level of the logic signal supplied to the ECL logic circuit 26 via a transmission line 22 from the CMOS logic circuit 12 to the logic level of the ECL logic circuit 26 and then apply it to the input of the ECL logic circuit, an input terminal 51 of a source-follower circuit 50 (consisting of an N-channel MOS transistor M50) is connected to an output of the CMOS logic circuit and an output terminal 53 of the source-follower 50 is connected to a sending end of the transmission line 22. A terminating resistor 24 has its one end connected to a receiving end of the transmission line 22 and its other end connected with a negative power supply V.sub.TT (typically -2V), so that at both of these ends is generated a DC-logic level (PECL level) with a logic amplitude of 800 milli-volts. This DC-logic level is AC-connected via a capacitor 25 to the input of the CMOS logic circuit 12, thus establishing an interface of the signal level between the CMOS logic circuit 12 performing logic operations on the positive power supply V.sub.DD and the ECL logic circuit 26 performing logic operations on the negative power supply; that is, the logic level of a logic signal output from the CMOS logic circuit 12 is level-shifted to a logic level matched to the logic operations of the ECL logic circuit 26.
In contrast to the first prior-art example for transmitting a signal in an AC manner, a second prior-art example shown in FIG. 5 transmits a logic signal to the ECL logic circuit 26 in a DC manner. That is, it is a level-shifting circuit 60 which is interposed, in configuration, between the CMOS logic circuit 12 and the ECL logic circuit 26 having the same configurations as those in the first example, so as to transmit the logic signal having an interfaced signal level to the input of the ECL logic circuit in the DC manner. Note here that this example assumes that the positive power Supply V.sub.DD is of 3V and the negative power supply is of -4.5V.
This level shifting circuit 60 includes an open-drain circuit 62, the transmission line 22 which has its sending end connected with an output terminal 63 of the open-drain circuit 62, and resistors R61 and R62 for Thevein-terminating, in configuration, the transmission line 22 between the ground potential at which the transmission line 22 is terminated and the negative power supply V.sub.TT (-2V). Thevenin termination here means that a combined resistance of the resistors R61 and R62 is made equal to a characteristic impedance value of the transmission line 22. The terminating end of the level shifting circuit 60 is directly connected to the input of the ECL logic circuit 26. Also, the open-drain circuit 62 consists essentially of an N-channel MOS transistor M62 which has its gate electrode connected with an input terminal 61 connected to the output of the CMOS logic circuit 12 and also its source electrode connected with the negative power supply V.sub.TT.
Thus, by Thevenin-terminating the transmission line 22 connected to the output of the open-drain circuit 62 between the ground potential and the negative power supply V.sub.TT using the resistors R61 and R62, to connect its terminating end directly to the input of the ECL logic circuit 26, thus enabling transmitting a signal to the above-mentioned ECL logic circuit 26 in the DC manner.
A third prior-art example shown in FIG. 6, like the second prior-art example, performs DC-wise transmission to the ECL logic circuit 26. That is, this example is a level shifting circuit which his disposed between the CMOS logic circuit 12 and the ECL logic circuit 26 having almost the same configuration as the first prior-art example, in such a configuration that the logic signal with the interfaced signal level may be transmitted to the input of the ECL logic circuit 26 in the DC manner. Note here that this example assumes that the positive power supply V.sub.DD is of 5V and the negative power supply, of -4.5V. This level shifting circuit 70 includes an N-channel MOS type inverter 72 which has its input terminal 71 connected with the output terminal of the CMOS logic circuit 12, a clamp circuit 74 connected to the output terminal of the N-channel MOS type inverter 72, a level shifting circuit 76 connected to the output terminal of the N-channel MOS type inverter 72, a source-follower circuit 78 connected to the output terminal of the level shifting circuit 76, the transmission line 22 which has its sending end connected to an output terminal 79 of the source-follower circuit 78, and a terminating resistor 80 which has its one terminal connected to a receiving end of the transmission line 22 and its other terminal connected to the negative power supply V.sub.TT (-2V).
The N-channel MOS type inverter 72 consists essentially of an N-channel MOS type transistor M72 and a resistor R72 in such a configuration that the N-channel MOS type transistor M72 has its gate connected to the input terminal 71, its source connected to the ground (GND), and its drain connected via the resistor R72 to the positive power supply V.sub.DD. The clamp circuit 74 consists essentially of a PN-junction diode D74 and a resistor R74 in such a configuration that the PN-junction diode D74 has its cathode connected via the resistor R74 to the output terminal of the N-channel MOS type inverter 72. The level shifting circuit 76 consists essentially of an NPN bipolar transistor Q76A, a resistor R76A, an NPN bipolar transistor Q76B, and a resistor R76B which are connected in series between the positive power supply V.sub.DD and the negative power supply V.sub.EE. The base of the NPN bipolar transistor Q76A is connected to the output terminal of the N-channel MOS type inverter 72, while the base of the NPN bipolar transistor Q76B is supplied with a V.sub.cs signal. The V.sub.cs signal consists essentially of a bias voltage for a constant current source. An NPN bipolar transistor Q78 which constitutes the source-follower circuit 78 has its base connected to the output of the level shifting circuit 76 (connection point between the resistor R76A and the collector of the NPN bipolar transistor Q76B), its collector connected to the ground, and its emitter connected to an output terminal 79 of the source-follower circuit 78. This output terminal 79 of the source-follower circuit 78 is connected to the sending end of the transmission line 22.
Thus, the signal level of a full-swing CMOS signal output from the CMOS logic circuit 12 is converted from the positive power supply V.sub.DD side into a signal with an amplitude level of approximately 800 milli-volts at the N-channel MOS type inverter 72 and the clamp circuit 74 and Shifted in level at the level shifting circuit 76 toward the negative power supply V.sub.TT and then shifted in level at the source-follower circuit 78 further toward the negative power supply V.sub.TT and also converted in impedance, so that a signal output from the source-follower circuit 78 is terminated via the transmission line 22 by the terminating resistor 80 connected to the negative power supply V.sub.TT. Across the terminating resistor 80 appears a signal level which can be decided by the ECL logic circuit 26, thus enabling DC-wise transmitting of a CMOS signal level to the ECL logic circuit 26.
The above-mentioned first prior-art example, however, has the problem that since the CMOS signal level output from the CMOS logic circuit 12 is level-converted at the level converting circuit 50 and supplied in an AC coupling to the input of the ECL logic circuit 26, the signal transmission is limited to some extent. For example, it may be necessary to scramble a signal to be transferred, that is, to combine a mark and a space such that a signal period of the mark (high level) and the space (low level) of the signal to be transmitted may not be as elongated as a time constant (which is decided by the electrostatic capacitance of the capacitor and the terminating resistance) or it may also be necessary to maintain the mark ratio (a ratio between the mark and the space of a signal to be transmitted) at 50% in an 8B10B encoding method. These measures are taken to prevent impossible logic decision caused by a shift of the signal level applied to the input of the ECL logic circuit 26 toward a bias voltage of the ECL logic circuit 26 in the case where the signal period of same code (for example, logic 0) continues for as long a time as the time constant when AC coupling is provided to the input of the ECL logic circuit 26.
Also, in the above-mentioned second and third prior-art examples, it may be necessary to apply a negative power supply voltage to the level converting circuit in order to provide DC-wise connection. In the case of the third prior-art example, moreover, it is necessary to apply the bias voltage V.sub.cs for a constant current source, so that a negative power supply must be equipped for that purpose. In an attempt to install in a mixed manner a level converting circuit as an ASIC (Application Specific IC) output buffer together with a CMOS logic circuit 12, this necessity of applying the negative power supply leads to a problem in power supply distribution that it is necessary to wire a negative power supply bus of the negative power supply in a periphery of the chip for supplying the negative power supply, a problem of inter-power supply ESD (Electro Static Discharge) protection that a reverse-bias ESD protection diode must be interposed between the positive power supply V.sub.DD and the negative power supply V.sub.TT, and a problem of a power supply application sequence that an order must be abided by in which the positive power supply V.sub.DD and the negative power supply V.sub.TT are applied.
These problems indicate that the level converting circuit of the second or third prior-art example cannot be used as is in a standard ASIC designing method, so that to use it in such a manner, there is no choice other than an approach of solving these problems in doing so. The level converting circuit of the second and third prior-art examples suffers a disadvantage of such a low affinity level that it can be used in the standard ASIC designing method only by taking special countermeasures whereby the above-mentioned problems can be avoided for that designing method.